Digital integrated circuits typically use a clock tree to distribute a clock signal from a source of the clock signal to various portions of logic on the integrated circuit that are clocked by the clock signal. In a typical integrated circuit, the circuitry that is to be clocked is not reconfigurable and does not change. The structure of the clock tree is therefore fixed at the time of manufacture of the integrated circuit and does not change regardless of how the integrated circuit is used. The physical and electrical characteristics of the clock tree are fixed. Accordingly, clock signal propagation times through the clock tree are fairly repeatable and predictable, regardless of the use to which the integrated circuit is put.
In a programmable logic device (PLD) such as a field programmable gate array (FPGA), however, the circuitry that is to be clocked can differ significantly from user design to user design. One user may wish to configure an FPGA such that a clock signal on the clock tree of the FPGA is used extensively in one part of the FPGA. Another user may wish to configure an identical FPGA such that a clock signal on the clock tree is not used at all in that part of the FPGA.
FIG. 1 (Prior Art) is a top-down diagram of an FPGA integrated circuit 1 that has a configurable clock tree 2. It is to be understood that the clock tree 2 is illustrative of one example of a clock tree on an FPGA, and that many different clock tree structures are employed in FPGA integrated circuits. In FIG. 1, the blocks 3 illustrated in dashed lines represent blocks of configurable logic. In one architecture, blocks of configurable logic are called configurable logic blocks (CLBs). Circuitry within the CLBs can be interconnected in a user-definable manner by a configurable interconnect structure (not shown). The configurable interconnect structure may, for example, be disposed in the areas between the various CLBs. Configurable clock tree 2 supplies a clock signal from a clock input terminal CLK 4 to parts of the FPGA circuitry that require the clock signal. In the illustrated example, clock tree 2 extends upward from terminal 4 and then branches to the left and right out across the surface of the integrated circuit. Clock drivers 5 are provided to drive the clock signal left and right down the clock tree branches.
In the example of FIG. 1, a user can configure FPGA 1 so that selected ones of the clock drivers 5 are disabled. This effectively cuts branches off the clock tree. Because switching clock drivers consume power, disabling clock drivers that drive clock lines that are not needed reduces power consumption of the overall functioning FPGA. Although disabling a part of the clock tree in this way to reduce power consumption may be advantageous from a power consumption point of view, it may in some FPGA designs change the electrical characteristics of the remaining part of the clock tree. Capacitive loading on the remaining part of the clock tree may, for example, be reduced. Changing the electrical characteristics of the remaining part of the clock tree may affect the signal transmission characteristics of the remaining part of the clock tree. This is generally undesirable. It is generally desired that signal propagation times in the clock tree be fairly predictable and constant regardless of how the FPGA is configured.
In addition to the ability to disable a part of the clock tree, FPGA 1 includes a number of programmable taps along each horizontally extending clock conductor of clock tree 2. If the clock signal is required extensively in an area of the FPGA, then the user may configure many programmable taps to tap the clock conductor many times in the localized area. On the other hand, if the clock signal is not required extensively in the localized area, then the user may configure the FPGA only to tap the clock conductor a relatively few number of times in that localized area. In FIG. 1, programmable taps that are configured to supply a clock signal from clock conductor 6 to corresponding local conductors (not shown) are illustrated as arrows.
FIG. 2 (Prior Art) illustrates two ways that such programmable tap structures can be realized. The first structure involves using a field effect transistor (FET) 7 to couple a clock signal on clock conductor 6 to a local clock conductor 8. To make this connection, FET 7 is turned on by a configuration bit stored in memory cell 9. Making this connection, however, increases the capacitive loading on clock conductor 6. When FET 7 is conductive and the clock signal on conductor 6 transitions low-to-high, current sourced from clock conductor 6 flows through the conductive FET 7 in order to charge the capacitance of local conductor 8. Similarly, when FET 7 is conductive and the clock signal transitions high-to-low, clock conductor 6 sinks current through FET 7 to discharge the capacitance of local conductor 8. As more and more of these local conductors are coupled to clock conductor 6, the loading on clock conductor 6 increases. The edge rate at which clock driver 5 can drive the clock signal down clock conductor 6 therefore decreases. This is undesirable because it is undesirable that clock signal propagation speeds in the clock tree change significantly depending on how the FPGA is configured.
Not only does the structure of FET 7 and memory cell 9 add loading to clock conductor 6 when FET 7 is turned on, but the structure also loads clock conductor 6 even if FET 7 is turned off. FET 7 has a parasitic capacitance between its source and drain as represented in FIG. 2 by capacitor symbol 10. Under high frequency AC conditions such as those present when a high frequency clock signal is present on clock conductor 6, the parasitic capacitance allows current flow between clock conductor 6 and local conductor 8, thereby loading clock conductor 6. The load on clock conductor 6 from many such FETs causes propagation through clock driver 5 to be undesirably slow.
A second conventional structure for tapping clock conductor 6 involves an inverter 11 in addition to a FET 12 and a memory cell 13. This structure further isolates the clock conductor 6 from an associated local clock conductor 14. Although this structure loads clock conductor 6 less than the structure involving FET 7, there still exists a parasitic capacitance (represented by capacitor symbol 15) associated with the transistors of inverter 11. Again, under high frequency AC conditions such as those present when a high frequency clock signal is present on clock conductor 6, the parasitic capacitance allows current to flow through or past inverter 11, thereby loading clock conductor 6. In addition, there are gate capacitances of the transistors within inverter 11. These capacitances, which are represented by capacitor symbols 16 and 17, are directly coupled to clock conductor 6. The gate capacitances 16 and 17 constitute additional loading on clock-conductor 6.
In FPGA 1, there are a great many local conductors that are programmably coupleable to clock tree 2. Each of these local conductors and/or its associated interconnection circuitry adds loading to the associated clock conductor of the clock tree. This is true even if the local conductors are not actually programmed to couple clock signals from the clock tree. Because there are so many such programmably coupleable local conductors, the clock conductors of such an FPGA clock tree can be significantly loaded. Not only are the clock conductors loaded, but propagation times through the clock tree may depend on how the FPGA is configured. If, for example, a first user configures an FPGA so that many of the programmable tap structures are enabled to tap a clock conductor at many locations, then loading on the clock conductor is greater and clock signal propagation times are slower. If, on the other hand, a second user configures an identical FPGA so that relatively few programmable tap structures are enabled to tap the clock conductor, then loading on the clock conductor is less and clock signal propagation times are faster. It is therefore seen that clock signal propagation delay through the clock tree depends on how the FPGA is configured. This is undesirable.